Dual-core microcontrollers from Texas instruments

Hello friends, this is going to be a jaw dropping article for you if you are not aware about dual core microcontrollers which Texas Instruments just launched. So read carefully.

xTMS320F28377D

Texas instruments has recently launched Delfino TMS320F2837xD device, which can be a game changer in the world of microcontrollers. This 32-bit floating point microcontroller has two cores working at 200MHz (5ns) and each core has a separate co-processor  that also works on 200MHz, so according to Texas instruments

Designers can realize up to 800 MIPS of total system performance.

This controller introduces a separate TMU (trigonometric math unit) which reduces number of cycles required to perform trigonometric functions. The TMS320F2837xD device also has a second-generation Viterbi Complex Math Unit (VCU II) with improved acceleration on Viterbi operations, complex multiplies, and the CRC engine.

A very good analog interface is maintained by  four 16-bit analog-to-digital converters (ADCs) as well as eight comparator subsystems.  In addition, the device has three 12-bit digital-to-analog converters (DACs).

The uPP is a high-speed, parallel data bus that allows direct connection to FPGAs or other devices with similar interfaces.

Here is the list of full specifications

  • Dual-Core Architecture
    • Two TMS320C28x 32-Bit CPUs
    • 200 MHz (5-ns Cycle Time)
    • IEEE 754 Single-Precision Floating-Point Unit (FPU)
    • Trigonometric Math Unit (TMU)
    • Viterbi/Complex Math Unit (VCU-II)
    • 16 x 16 and 32 x 32 MAC Operations
    • 16 x 16 Dual MAC
    • Three 32-Bit CPU Timers per Core
    • Harvard Bus Architecture
    • Fast Interrupt Response and Processing
    • Unified Memory Programming Model
  • Two Programmable Control Law Accelerators
    • 200 MHz (5-ns Cycle Time)
    • 32-Bit Floating-Point Math Accelerator
      (IEEE 754 Single Precision)
    • Executes Code Independently of Main CPU
  • On-Chip Memory
    • Up to 1MB Flash, Up to 204KB RAM
    • Boot ROM (64KB)
      • SPI, I2C, CAN, and Parallel I/O Software Boot Modes
      • Standard Math Tables
  • System Peripherals
    • Dual 32- and 16-Bit EMIF With ASRAM and SDRAM Support
    • Dual 6-Channel DMA Controller
    • Up to 169 Individually Programmable, Multiplexed GPIO Pins With Input Filtering
  • Communications Peripherals
    • USB 2.0 + PHY Port
    • Support for 12-Pin 3.3 V-Compatible Universal Parallel Port (uPP) Interface
    • Two CAN-Bus Ports (32 Mailboxes Each)
    • Three High-Speed (40-MHz) SPI Ports With 16-Level FIFO, DMA Support, and
      CLA-Accessible
    • Two Multichannel Buffered Serial Ports
    • Four Serial Communications Interfaces
    • Two Inter-Integrated Circuit (I2C) Interfaces
  • Analog Subsystem
    • Four Dual-Mode Analog-to-Digital Converters
    • 16-Bit Mode
      • 1.1 MSPS Each (Up to 4.4-MSPS System)
      • Differential
      • External Reference
      • Up to 12 External Channels
    • 12-Bit Mode
      • 3.5 MSPS Each (Up to 14-MSPS System)
      • Single-Ended or Differential
      • External Reference
      • Up to 24 External Channels
    • Single Sample-and-Hold (S/H)
      (Four-Simultaneous-S/H System)
    • Integrated Post-Processing of ADC Conversions
      • Saturating Offset Calibration
      • Error From Setpoint Calculation
      • High, Low, and Zero-Crossing Compare, With Interrupt Capability
      • Trigger-to-Sample Delay Capture
    • Analog Comparator/Digital-to-Analog Converter (DAC) Subsystem With Glitch Filter, for Windowed Trip Monitor and PCMC Interfaces
      • Eight Windowed Comparators With 12-Bit DAC References
    • Three 12-Bit Buffered DAC Outputs
  • Enhanced Control Peripherals
    • 24 PWM Channels With Enhanced Features
    • 16 High-Resolution PWM Channels
      • High-Resolution on Both A and B Channels of 8 PWM Modules
      • Dead-Band Support (on Both Standard and High-Resolution)
    • Six Capture Modules
    • Three Quadrature Encoder Pulse (QEP) Modules
    • Two Sigma-Delta Filter Modules (SDFMs) With up to 8 Input Channels, Plus PWM Synchronization
  • Expanded Peripheral Interrupt (ePIE) Block
    • Supports up to 192 Peripheral Interrupts
    • GPIO Pins can be Connected to 5 Core Interrupts
  • JTAG Boundary Scan Support
  • Advanced Emulation Features
    • Analysis and Breakpoint Functions
    • Two Hardware Breakpoints per CPU
    • Real-Time Debug via Hardware
  • Independent Dual-Zone Security per CPU
    • 128-Bit Security Key and Lock
    • Protects Flash, OTP, and RAM Blocks
  • Safety and Reliability Features
    • ECC on Flash, ECC or Parity on RAMs
    • Missing Clock Detection
    • Self-Test and Real-Time Self-Test BIST
  • Low-Power Modes and Power Savings
    • IDLE, STANDBY, HALT, and HIBERNATE Modes Supported
    • Disable Individual Peripheral Clocks
  • Clock and System Control
    • Two Internal Zero-Pin 10-MHz Oscillators
    • On-Chip Crystal Oscillator/External Clock Input
    • Dynamic PLL Ratio Changes Supported
    • Watchdog Timer Module
    • Missing Clock Detection Circuitry
  • 1.2-V Core, 3.3-V I/O Design

Here is the link to texas instruments website which gives a glimpse of different features.

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